Method and a Computer Readable Medium for Analyzing a Design of an Integrated Circuit

ABSTRACT

A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value.

FIELD OF THE INVENTION

The present invention relates to a method and a computer readable mediumfor analyzing a design of an integrated circuit and especially forstatic timing analysis.

BACKGROUND OF THE INVENTION

Modern integrated circuits include a very large amount of logic circuitssuch as flip flops, logic gates and the like. The design process isrelatively long and includes multiple stages such as high leveldescription, synthesis, placement and routing, extraction, static timinganalysis and the like.

Various vendors provide software tools capable of performing statictiming analysis. These tools include, for example, Quartus® II ofAltera™, of California U.S.A.; Timer™ of Actel™ of California, U.S.A.,and PathMill® and PrimeTime™ of Synopsys™ of California, U.S.A.

Various verification and re-design stages are required before the designprocess is completed. Typically, the synthesis is responsive to designconstraints (including timing constraints) and to the characteristics ofdesigned components. The characteristics of multiple designed componentsare usually gathered in a cell library. Various vendors offer standardcell libraries, including Libra-Visa of Synopsys.

The following U.S. patent applications, all being incorporated herein byreference, illustrate various prior art cell libraries: U.S. patentapplication publication number 20050006670 of Zounes, U.S. Patentapplication publication number 20040237059 of Chen et al., U.S. patentapplication publication number 20040218831 of Liu, U.S. patentapplication publication number 20040195690 of Flohr, U.S. patentapplication publication number 20040143797 of Nguyen et al., U.S. patentapplication publication number 20040040004 of Sakiyama et al., and U.S.patent application publication number 20030149953 of Whitaker et al.

In general, it is harder to correct design errors during later stages ofthe design process, and especially after the placement and routingstages.

Static timing analysis usually includes analyzing, debugging andvalidating the timing performance of a design of an integrated circuit.During this stage the timing associated with the propagation of signalsthrough a designed integrated circuit are calculated. Especially, thisanalysis checks whether the delay of a component fits the clockfrequency requirements, and whether hold and setup violations occurred.

U.S. Pat. No. 6,591,407 of Kaufman et al., U.S. Pat. No. 5,768,159 ofBelkadi et al., U.S. Pat. No. 6,237,127 of Craven et al., U.S. patentapplication publication number 2001/007144 of Terazawa, and PCT patentapplication publication number WO0075815 titled “An arrangement and amethod relating to design of circuits”, all being incorporated herein byreference, provide an overview of static timing analysis.

A hold violation is determined by checking if a data or a control inputsignal that is provided to a certain component was steady for at least apredefined period (referred to as a worst case hold time) relative to acorresponding clock event occurred. A clock event is usually a rising orfalling edge of the clock signal.

A setup violation is determined by checking if a data or a control inputsignal that is provided to a certain component was steady for at least apredefined period (referred to setup period) before a correspondingclock event occurred.

The worst case hold time guarantees that regardless of the setup timethe component will operate in a proper manner.

There is a need to provide an effective method for static timinganalysis.

SUMMARY OF THE PRESENT INVENTION

A method and a computer readable medium for analyzing a design of anintegrated circuit, as described in the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with thedrawings in which:

FIG. 1 illustrates an exemplary circuit;

FIG. 2 illustrates a method for analyzing a design of an integratedcircuit, according to an embodiment of the invention;

FIG. 3 illustrates various timing diagrams, according to an embodimentof the invention;

FIG. 4 illustrates a method for analyzing a design of an integratedcircuit, according to an embodiment of the invention;

FIG. 5 illustrates a method for defining a cell library, according to anembodiment of the invention;

FIG. 6 illustrates an integrated circuit design process, according to anembodiment of the invention;

FIG. 7 illustrates a design station, according to an embodiment of theinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following figures illustrate exemplary embodiments of the invention.They are not intended to limit the scope of the invention but ratherassist in understanding some of the embodiments of the invention. It isfurther noted that all the figures are out of scale.

FIG. 1 illustrates an exemplary circuit 10. Circuit 10 includes multiplecomponents such as D-type flip-flops 20, 22 and 24, as well asadditional circuitries 30 and 32 that are connected between the flipflops. It is assumed that all flip flops 20, 22 and 24 receive the sameclock signal and that the clock signals provided to the different flipflops are not skewed. This is not necessarily so. It is further notedthat components other than flip flops can be analyzed and that the celllibrary can include cells other than flip flops. Typically such alibrary also includes logic gates.

Each flip flop can be characterized by multiple pairs of setup times andhold times. Conveniently, longer hold times are associated with shortersetup times. For example, the inventors found that very long setup timesare associated with relatively short hold times. Conveniently, the sumof one pair of setup time and its associated hold time differs from asum of another pair of setup time and its associated hold time.

It is noted that flip flops 20, 22 and 24 can be characterized by thesame mapping between multiple setup times and hold times, but this isnot necessarily so.

It is further noted that multiple setup time and hold time pairs of acertain component can be fed into a design station in various manners.

Multiple circuits such as circuit 10 are usually included within anintegrated circuit that can be, for example, a processor, a system onchip. The integrated circuit can be included within a large range ofsystems of objects such as but not limited to a stationary device or amobile device, such as but not limited to a cellular phone, a personaldata accessory, a computer, a vehicle, a satellite, and the like.

It is further noted that circuit 10 can be a part of a boundary scanregister that is activated by a relatively slow clock in which holdviolation (rather then setup violation) occur, but this is necessarilyso.

FIG. 2 illustrates a method 100 for analyzing a design of an integratedcircuit, according to an embodiment of the invention.

Method 100 conveniently starts by stage 110 of defining, for at leastone designed component of the integrated circuit, a mapping betweenmultiple hold values and multiple setup values. Many (or all) componentscan be associated with such a mapping, while other components can becharacterized by a single setup time and a single hold time.

Conveniently, the overall period during which a control or data signalhas to be stable is not fixed. A sum of first setup time and acorresponding hold time is not necessarily the same as another sum ofanother setup time and a corresponding hold time. Conveniently, therelationship between the setup times and the hold times is non-linear.

According to various embodiments of the invention, once the mapping isdefined it can be associated with a certain component in variousalternative ways. According to one embodiment of the invention stage 110can be followed by stage 120 of defining at least one component byassociating it with multiple hold times and multiple setup times. Thus,in a cell library at least one cell definition can include thesemultiple setup and hold times.

According to another embodiment of the invention stage 110 is followedby stage 130 of associating a single pair of setup time andcorresponding hold time with each designed component. Thus, if there areK different pairs of setup time and hold time, K different componentsare defined in the cell library. It is noted that according to yet afurther embodiment of the invention M cells can be defined wherein K>M.

Either one of stage 110-130 is not executed for any design process.These stages are rather preliminary stages that are executed during thedefinition of a cell library. The cell library can be used duringmultiple design processes of multiple integrated circuits.

Either one of preliminary stages 110-130 is followed by stage 200 ofdefining possible timings of signals to be provided to the integratedcircuit. This stage includes defining possible time windows during whichsignals can be provided to the integrated circuit. Typically, there aretiming limitations imposed upon the provision of signals to theintegrated circuit. The amount of typical scenarios can be very largebut finite.

It is noted that the setup times and hold times can be responsive toadditional parameters such as voltage, temperature and the like. Thecell library can also include this relationship. According to anotherembodiment of the invention the cell library can include the worst setuptime and/or the worst hold times for a range of possible temperaturesvalues. The cell library can also include the worst setup time and worsthole times for a range of possible voltage supply values, and/or acombination of voltage supply and temperature values. Alternatively, thedependency between voltage and/or temperature and a range of possiblesetup times and/or hold times can be represented by few (even a single)setup times or hold times. This representation does not necessarilyinclude the worst case scenario.

Stage 200 is followed by stage 240 of determining relationships betweenclock events and corresponding data/control events that ideally precedethe clock events, in response to the possible timing of signals. Adata/control event can be a control event or a data event or acombination of both. Such an event occurs when at least one data and/orcontrol signal changes.

Stage 240 conveniently includes determining the timing of signalpropagation through the designed integrated circuit and especiallydetermining for at least one designed component, and for multiplepossible signals arrival times, at least one shortest time periodbetween an occurrence of a clock event and an occurrence of thecorresponding data (or control) event.

Assuming, for example that: (i) flip flop 20 can receive a data signalfrom an integrated circuit pin during a first timing window, (ii) flipflop 20 is triggered by a rising edge of a clock signal that can occurduring a second timing window, and (iii) a rising edge of the datasignal has to precede the clock signal. Given these assumptions stage240 can include calculating the shortest time period between the risingedge of that data signal and the rising edge of the data signal.

It is noted that in many cases a certain component can receive (i) afirst data or control signal that propagates through a first path, (ii)a second data or control signal that propagates through a second path,and (iii) a clock signal that propagates through a third path. In thiscase stage 240 conveniently includes calculating the time period betweenthe latest data or control signal change and the earliest clock event.Stage 240 can include determining the setup time of each component. Thissetup time is conveniently the shortest setup time of each componentthat is still longer than the shortest time period between the change ofthe control or data signal and the corresponding clock signal. If nosuch setup time if found then setup violation occurs and has to becorrected.

Stage 240 is followed by stage 260 of determining at least one holdparameter in response to the relationships. This stage convenientlyincludes using the mapping between multiple setup values and themultiple hold times and finding the hold time that corresponds to thesetup time found in stage 240.

Stage 260 is followed by stage 280 of calculating hold violations bycomparing the hold times determined during stage 260 to the relativetimings of clock signals and corresponding data or clock signals. Therelative timing can include the shortest period between a clock eventand a following data or control change.

Stage 280 is followed by stage 300 of correcting hold violation.Conveniently, stage 300 also includes correcting setup violations.

Stage 300 can include at least one of the following stages: (i)replacing one component by another component from the cell library thatdiffers by its setup time or its hold time from the replaced component,(ii) introducing a delay within the path of the data or control signalthat caused a hold violation, (iii) introducing multi-cycle paths, andthe like.

Stage 300 can be followed by stage 240 such that stages 240-300 arerepeated until the timing violations are corrected. The repetition canalso be responsive to another or to an alternative control criterion,such as the amount of iterations, and the like.

It is noted that usually the timing conditions of all components of adesigned integrated circuit are checked, in view of all the possibletiming constraints imposed on input signals to the designed integratedcircuit.

FIG. 3 illustrates various timing diagrams 61, 62, 71 and 72, accordingto an embodiment of the invention. For simplicity of explanation therising period and falling period of each signal was assumed to benegligible.

It is noted that in some cases the rising period and/or falling periodare taken into account when determining setup an/or hold violations.

According to an embodiment of the invention there is provided a mappingbetween setup times, hold times and relevant rising or falling periodsof the corresponding signals. If, for example a device is triggered by arising edge of the clock and the corresponding data raises before therising edge of the clock and is negated after the rising edge of theclock the setup violation is responsive to the rising period of theclock signal and the rising period of the data signal. A hold violationis determined in view of the setup period, the rising period of theclock signal and the falling period of the data signal.

The timing diagrams illustrate various timing windows of various clockand data signals that arrive to flip flop 20. Each timing window isillustrated by the earliest signal and the latest signal that define thetiming window.

It is assumed that flip flop 20 is triggered by the rising edge of clocksignal CLK 60 and that it also receives a data signal D 70. The risingedge of CLK 60 can arrive to the clock input of flip flop 20 between T3and T4, as illustrated by lines 61 and 62. The rising edge of CLK 60 isa clock event.

The rising edge (data event) of data signal D 70 can arrive to the datainput of flip flop 20 between T1 and T2, and can be negated (anotherdata event) between T5 and T6, as illustrated by lines T1 and T2. It isnoted that this signal can be first negated and the asserted.

Table 1 illustrates the multiple setup times and hold times thatcharacterized flip flop 20:

Setup time Hold time SU1 H1 SU2 H2 SU3 H3 SU4 H4

These values are not responsive to clock skews. Clock skews can shiftthe timing of signals that are later compares to the setup and holdtimes. It is also assumed that: (i) SU1<SU2<SU3<SU4, (ii) H1<H2<H3<H4,(iii) that (SU1+H1) differs from at least one of the following sums:(SU2+H2), (SU3+H3) or (SU4+H4), and that (iv) the ratio (SU1/SU2)differs from at least one of the following ratios: (H1/H2), (H2/H3) or(H4/H3).

Given this set of assumptions stage 240 may include determining theshortest period between the assertion of the data signal D 70 and therising edge of CLK 60. This period is T3-T2.

Stage 240 may also include calculating the shortest setup period out ofSU1-SU4 that is still shorter than T3-T2. If such a setup period is notfound that there is a need to correct this setup violation by variousmeans including delays, cell replacement and the like. Assuming thatsuch a set up period is found and that it is SU2 then stage 260, thatfollows stage 240, includes selecting H2 as the relevant hold time.

Stage 260 is followed by stage 280 of calculating hold violations bycomparing the relevant hold time H2 to the timing difference between thelatest possible CKL 60 rising edge (T4) and the earliest negation of D70 (T5).

If (T5-T4) is shorter that H2 then a hold violation occurred. It isnoted that if (T5-T4) is shorter than H4 but is longer than H2 than ahold violation does not occur, although prior art methods woulddetermine that a hold violation occurred and perform an unnecessary holdviolation correction stage.

FIG. 4 illustrates a method 400 for analyzing an design of an integratedcircuit, according to an embodiment of the invention.

Method 400 starts by stage 110 of defining, for at least one designedcomponent of the integrated circuit, a mapping between multiple holdtimes and multiple setup times. This mapping is not responsive to clockskews.

Conveniently, stage 110 can be followed by optional stage 120 or 130.

Either one of stages 110-130 can be followed by stage 280 of calculatinghold violations in response to the mapping.

FIG. 5 illustrates method 500 for defining a cell library, according toan embodiment of the invention.

Method 500 starts by stage 510 of defining at least one internal delayof a designed component.

Stage 510 is followed by stage 520 of providing a cell that ischaracterized by multiple hold times and multiple setup values. Therelationship between these times is not responsive to clock skews.Conveniently, the period during which a signal has to be stable is notfixed. A sum of first setup time and a corresponding hold time is notnecessarily the same as a another sum of another setup time and acorresponding hold time. Conveniently, the relationship between thesetup times and the hold times is non-linear.

According to various embodiments of the invention, once the mapping isdefined it can be associated with a certain component in variousalternative ways. Some of these ways are illustrated in relation tostage 110 of FIG. 2.

FIG. 6 illustrates an integrated circuit design process 600, accordingto an embodiment of the invention.

Process 600 starts by stage 610 of high level circuit design. This stagecan include using a high level design language such as Verilog, RTL andthe like. Stage 610 is followed by stage 620 of design synthesis, givenvarious timing constraints (possible timings of signals to be providedto the integrated circuit), and given a cell library.

The cell library or at least some of the cells of the cell library canbe defined by using stages 110-130 or stages 510-520. Some of thecontent of the cell library can be determined in prior art manners, suchas receiving a standard cell library, using predefined cell librariesand the like.

Stage 620 is followed by stage 630 of performing placement and routing.

Stage 630 is followed by stage 640 of performing static timing analysis.According to an embodiment of the invention stage 640 can includesinclude various stages of method 100 or method 400. According to anotherembodiment of the invention these stages can be applied in combinationwith prior art static timing analysis stages.

According to yet another embodiment of the invention stage 640 caninclude stage 642 of performing a prior art static timing analysis basedupon worst case hold time and setup time and receiving timingviolations. Stage 642 is followed by stage 644 of determining, inresponse to the possible timing of signals arriving to the components,the appropriate setup times and the corresponding hold times. Stage 644can include stage 240.

Stage 644 is followed by stage 300 of correcting timing violations.

FIG. 7 illustrates a design station 710, according to an embodiment ofthe invention.

The design station can be a stand-alone station or part of a network ora group of design station.

The design station is illustrated, for convenience of explanation as adesktop computer 710 that includes a processor 720 as well as a computerreadable medium 700 that stores a set of instructions to be executed bythe processor 720. The processor 720 can access a cell library 750during the various design stages.

It is noted that many design station configurations are known in the artand can be applied. The design can be implemented by many designers thathave access to multiple design stations that in turn can access remotestorage devices that can store cell libraries, instructions, integratedcircuit designs and the like.

According to various embodiments of the invention the mentioned abovemethods (100, 400, 500, 600) can be executed by a processor thatexecuted a set of instructions that is stored within a computer readablemedium. This medium can include magnetic storage devices (such asmagnetic tape, diskettes, disk drives), optical storage devices (such asDVD, CD) and the like. The processor can execute the method incooperation with other components such as storage unit, buses and thelike.

According to an embodiment of the invention a computer readable mediumis provided having stored thereon a set of instructions, the set ofinstructions, when executed by a processor, cause the processor todefine possible timings of signals to be provided to the integratedcircuit, to determine relationships between clock events andcorresponding data/control events that ideally precede the clock events,in response to the possible timing of signals, and determine holdparameters in response to the relationships and to calculate holdviolations.

According to an embodiment of the invention a computer readable mediumis provided having stored thereon a set of instructions, the set ofinstructions, when executed by a processor, cause the processor todefine, for at least one designed component of the integrated circuit, amapping between multiple hold times and multiple setup values, and tocalculate hold violations.

According to an embodiment of the invention a computer readable mediumis provided having stored thereon a set of instructions, the set ofinstructions, when executed by a processor cause the processor to definecell that is characterized by multiple hold times and multiple setuptimes.

Variations, modifications, and other implementations of what isdescribed herein will occur to those of ordinary skill in the artwithout departing from the spirit and the scope of the invention asclaimed. Accordingly, the invention is to be defined not by thepreceding illustrative description but instead by the spirit and scopeof the following claims.

1. A method for analyzing a design of an integrated circuit, the methodcomprises: defining possible timings of signals to be provided to theintegrated circuit and calculating hold violations; defining, for atleast one designed component of the integrated circuit, a mappingbetween multiple hold values and multiple setup values for a certainclock skew value; determining relationships between clock events andcorresponding data/control events that ideally precede the clock events,in response to the possible timing of signals, determining holdparameters in response to the relationships; and correcting holdviolations.
 2. The method according to claim 1 wherein the determiningthe relationships comprises determining, for at least one designedcomponent, and for multiple possible timings of signals, at least oneshortest time period between an occurrence of a clock event and anoccurrence of the corresponding data/control event.
 3. The methodaccording to claim 1 wherein the defining comprises defining a mappingbetween multiple hold values and multiple setup values, wherein themultiple setup times and the multiple hold times are responsive to atemperature parameter.
 4. The method according to claim 3 wherein thecorrecting comprises replacing one component by another component thatdiffers by its setup time or its hold time from the replaced component.5. The method according to claim 1 wherein the defining comprisesdefining a mapping between multiple hold values and multiple setupvalues, wherein the multiple setup times and the multiple hold times areresponsive to a temperature parameter.
 6. The method according to claim1 wherein the defining comprises defining a mapping such that a sum offirst setup time and a corresponding hold time differs from another sumof another setup time and a corresponding hold time.
 7. The methodaccording to claim 1 wherein the defining comprises defining a mappingsuch that the relationship between the setup times and the hold times isnon-linear.
 8. The method according to claim 1 further comprisingdefining at least one component by multiple hold times of the designedcomponent and multiple setup times of the designed component for acertain clock skew value.
 9. The method according to claim 1 furthercomprising defining associating a single pair of setup time andcorresponding hold time with each designed component.
 10. A method foranalyzing a design of an integrated circuit, the method comprises:calculating hold violations; defining, for at least one designedcomponent of the integrated circuit, a mapping between multiple holdtimes and multiple setup values for a certain clock skew value; whereinthe defining comprises defining a mapping such that the relationshipbetween the setup times and the hold times is non-linear.
 11. The methodaccording to claim 9 wherein the defining comprises defining a mappingsuch that a sum of first setup time and a corresponding hold timediffers from another sum of another setup time and a corresponding holdtime.
 12. The method according to claim 9 further comprising defining atleast one component by multiple hold times values of the designedcomponent and multiple setup times of the designed component.
 13. Themethod according to claim 9 wherein the relationship between the setuptimes and the hold times of at least one designed component isnon-linear wherein very long setup times are associated with relativelyshort hold times.
 14. The method according to claim 9 furthercomprising: defining at least one internal delay of a designedcomponent.
 15. The method according to claim 12 wherein the definingcomprises defining the mapping such that a sum of first setup time and acorresponding hold time differs from another sum of another setup timeand a corresponding hold time.
 16. A computer readable medium havingstored thereon a set of instructions, the set of instructions, whenexecuted by a processor, cause the processor to: define, for at leastone designed component of the integrated circuit, a mapping betweenmultiple hold values and multiple setup values for a certain clock skewvalue; define possible timings of signals to be provided to theintegrated circuit and calculate hold violations; determinerelationships between clock events and corresponding data/control eventsthat ideally precede the clock events, in response to the possibletiming of signals; determine hold parameters in response to therelationships; and correct hold violations.
 17. The computer readablemedium according to claim 16 wherein the set of instructions furthercause the processor to determine, for at least one designed component,and for multiple possible timings of signals, at least one shortest timeperiod between an occurrence of a clock event and an occurrence of thecorresponding data/control event.
 18. The computer readable mediumaccording to claim 16 wherein the set of instructions further cause theprocessor to define a mapping such that the relationship between thesetup times and the hold times is non-linear.
 19. (canceled)
 20. Thecomputer readable medium according to claim 16, wherein the set ofinstructions further cause the processor to define at least one internaldelay of a designed component.
 21. The method according to claim 2wherein the defining comprises defining a mapping between multiple holdvalues and multiple setup values, wherein the multiple setup times andthe multiple hold times are responsive to a temperature parameter.